Workload-based adjustable cache size

ABSTRACT

A workload level associated with an expandable data buffer is determined, where the expandable data buffer and an expandable mapping table cache are stored in internal memory and the expandable mapping table cache is used to store a portion of a mapping table that is stored on external storage. An amount of internal memory allocated to the expandable data buffer and an amount of internal memory allocated to the expandable mapping table cache are adjusted based at least in part on the workload level.

CROSS REFERENCE TO OTHER APPLICATIONS

This application claims priority to U.S. Provisional Patent ApplicationNo. 62/001,781 entitled WORKLOAD-BASED DYNAMIC L2 CACHE-SIZING filed May22, 2014 which is incorporated herein by reference for all purposes.

BACKGROUND OF THE INVENTION

Solid state storage (e.g., NAND storage) is becoming increasinglypopular. In particular, solid state storage is attractive for mobilesystems, because solid state storage is able to be incorporated intosmaller systems compared to some other types of storage, such asmagnetic storage. It would be desirable if the performance of suchsystems could be improved. For example, it would be desirable if theamount of time required to read data from solid state storage in amobile system could be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments of the invention are disclosed in the followingdetailed description and the accompanying drawings.

FIG. 1 is a diagram illustrating an embodiment of a solid state storagesystem which includes an expandable mapping table cache.

FIG. 2 is a flowchart illustrating an embodiment of a workload-based,internal memory reallocation process.

FIG. 3 is a diagram illustrating an embodiment of various allocations ofinternal memory to an expandable mapping table cache and an expandabledata buffer.

FIG. 4 is a flowchart illustrating an embodiment of a process fordetermining a workload level.

FIG. 5 is a flowchart illustrating an embodiment of a workload-based,internal memory reallocation process which takes into consideration hitcounts associated with cache entries that have been evicted.

FIG. 6 is a diagram illustrating an embodiment of hit counters and anassociated set of current, most recently evicted cache entries.

FIG. 7 is a diagram illustrating an embodiment of incremented hitcounters at various points in time.

FIG. 8 is a flowchart illustrating an embodiment of a process fortracking hit counts.

FIG. 9 is a flowchart illustrating an embodiment of a process foradjusting an amount of internal memory allocated based at least in parton hit counts.

FIG. 10 is a diagram illustrating an embodiment of an LRU window whichincludes dirty entries and clean entries.

FIG. 11 is a flowchart illustrating an embodiment of a workload-based,internal memory reallocation process that uses a sorted, doubly-linkedlist.

FIG. 12 is a diagram illustrating an embodiment of dirty page countswhich are used to sort dirty entries in an LRU window.

DETAILED DESCRIPTION

The invention can be implemented in numerous ways, including as aprocess; an apparatus; a system; a composition of matter; a computerprogram product embodied on a computer readable storage medium; and/or aprocessor, such as a processor configured to execute instructions storedon and/or provided by a memory coupled to the processor. In thisspecification, these implementations, or any other form that theinvention may take, may be referred to as techniques. In general, theorder of the steps of disclosed processes may be altered within thescope of the invention. Unless stated otherwise, a component such as aprocessor or a memory described as being configured to perform a taskmay be implemented as a general component that is temporarily configuredto perform the task at a given time or a specific component that ismanufactured to perform the task. As used herein, the term ‘processor’refers to one or more devices, circuits, and/or processing coresconfigured to process data, such as computer program instructions.

A detailed description of one or more embodiments of the invention isprovided below along with accompanying figures that illustrate theprinciples of the invention. The invention is described in connectionwith such embodiments, but the invention is not limited to anyembodiment. The scope of the invention is limited only by the claims andthe invention encompasses numerous alternatives, modifications andequivalents. Numerous specific details are set forth in the followingdescription in order to provide a thorough understanding of theinvention. These details are provided for the purpose of example and theinvention may be practiced according to the claims without some or allof these specific details. For the purpose of clarity, technicalmaterial that is known in the technical fields related to the inventionhas not been described in detail so that the invention is notunnecessarily obscured.

FIG. 1 is a diagram illustrating an embodiment of a solid state storagesystem which includes an expandable mapping table cache. In the exampleshown, host 100 communicates with storage controller 110, which in turncommunicates with solid state storage 120. In some embodiments, storagecontroller 110 comprises a semiconductor device, such as anapplication-specific integrated circuit (ASIC) or a field-programmablegate array (FPGA)). For simplicity, solid state storage 120 is shown asa single device, but in some embodiments solid state storage 120comprises multiple semiconductor devices. In some embodiments, solidstate storage 120 includes NAND Flash.

In the example shown, host 100 sends read instructions and writeinstructions (not shown) to storage controller 110 which include logicaladdresses, specifically logical block addresses (at least in thisexample). In contrast, the read instructions and write instructions (notshown) passed from storage controller 110 to solid state storage 120include physical addresses.

To keep track of what physical addresses correspond to what logicalblock addresses, a mapping table is used to store the mapping. Solidstate storage systems in particular must keep track of the mappingbetween logical addresses and physical addresses compared to some othertypes of storage systems (e.g., magnetic storage) because of the accesscharacteristics specific to solid state storage. Unlike magneticstorage, for example, solid state storage does not support in-placeupdates because the erase operation can only take place on a blockbasis, where a block contains many logical block addresses (e.g., 1024).As such, data which is to be overwritten is simply marked as invalid,and the new data sequence is written elsewhere. Over time, many logicalblock addresses in a given block become invalid and eventually theremaining valid data is moved to another location so that the block canbe reclaimed. This operation is known as garbage collection. As aresult, the physical address(es) which correspond to a given logicalblock address change over time as data becomes invalid and garbagecollection is performed. Therefore, the storage controller must manage alogical to physical mapping table.

In embodiments described herein, the storage controllers have arelatively small amount of internal memory, so the entire mapping tablecannot be kept on the storage controller. For example, a mapping tablewill be about 0.1% the size of the storage, so a 256 GB solid statestorage drive will require a mapping table of 256 MB. In eMMC and UFSapplications, a mapping table of that size is too big to be stored inits entirety in internal memory. As such, mapping table 122 is stored onsolid state storage 120.

To improve performance, a cache (116) is stored in internal memory 112which is used to store part of mapping table 122. This cache is referredto herein as an expandable mapping table cache. The cache is called anexpandable cache because it is able to be expanded depending (at leastin part) upon the workload of the system. More specifically, internalmemory is reallocated from expandable data buffer 114 to expandablemapping table cache 116 when the workload of the system is light andexpandable data buffer 114 is at least partially unused. In variousembodiments, expandable data buffer 114 is a write buffer (e.g., forbuffering write data received from host 100 before the write data iswritten to solid state storage 120) or a read buffer (e.g., for storingpre-fetched read data from solid state storage 120 that host 100 has notyet asked for but may ask for in the future). In one example whereexpandable data buffer 114 is a write buffer, some of the write bufferis reallocated to cache the mapping table if the write buffer ispartially or completely empty and the system is in a short write mode(e.g., because the last write instruction received from host 100 is ashort, non-burst write). If the write workload gets heavier (e.g.,because host 100 starts sending more write instructions and/or largerwrite instructions to storage controller 110), internal memory can bereallocated from expandable mapping table cache 116 to expandable databuffer 114 to handle the heavier write workload.

Internal memory controller 118 is responsible for adjusting the size ofexpandable data buffer 114 and expandable mapping table cache 116 basedon the workload level and, in some embodiments, other factors. Forexample, internal memory controller 118 will monitor the workload levelby monitoring (e.g., continually and/or in real time) the instructionssent from host 100 to storage controller 110 and/or the degree to whichexpandable data buffer 114 is occupied to get a sense of the workloadlevel. Depending upon the determined workload level (and, as describedabove, other factors in some embodiments), internal memory controller118 adjusts the amount of internal memory allocated to expandable databuffer 114 and expandable mapping table cache 116. In some embodiments,the total amount of internal memory allocated to expandable data buffer114 and expandable mapping table cache 116 remains constant, so thatexpandable data buffer 114 would be increased by the same amount ofmemory that expandable mapping table cache 116 is decreased by, and viceversa.

In some embodiments, internal memory controller 118 also tracks thenumber of hits for cache entries that have been recently evicted fromthe cache. These hit counts are used (e.g., in addition to the workloadlevel) to decide whether to increase the size of expandable mappingtable cache 116 (e.g., assuming that the workload level and the amountof unused expandable data buffer permit such an expansion). To put itanother way, internal memory controller 118 will decide whether thecache hit rate is likely to increase if the size of the cache isincreased. There is typically a non-zero cost associated withreallocating internal memory from the data buffer to the cache, so itmay be desirable to do a cost-benefit analysis.

In some embodiments, expandable mapping table cache 116 keeps track ofcache entries which are less expensive to discard (e.g., when internalmemory controller 118 decides to reallocate internal memory from cache116 to buffer 114) versus cache entries that are more expensive todiscard. In such embodiments, cache entries that are less expensive todiscard are discarded first when expandable mapping table cache 116 isdownsized; once all of the less expensive cache entries have beendiscarded, then the more expensive cache entries are discarded.

For clarity, some elements not directly related to the technique are notshown herein. For example, the data stored on solid state storage 120 isnot shown, nor does storage controller 110 show an error correctionencoder/decoder, which is a common component in storage controllers.This is not intended to be limiting and real-world embodiments of thesystem may include components which are not shown herein, such as errorcorrection encoders/decoders, etc.

FIG. 2 is a flowchart illustrating an embodiment of a workload-based,internal memory reallocation process. In the example shown, one exampleof the monitoring and reallocation performed by internal memorycontroller 118 in FIG. 1 is shown.

At 200, a workload level associated with an expandable data buffer isdetermined, wherein the expandable data buffer and an expandable mappingtable cache are stored in internal memory and the expandable mappingtable cache is used to store a portion of a mapping table that is storedon external storage. In FIG. 1, for example, internal memory controller118 determines a workload level associated with expandable data buffer114. In that example, expandable data buffer 114 and expandable mappingtable cache 116 are both stored on internal memory 112. Expandablemapping table cache 116 stores part of mapping table 122 (not shown)which is located on solid state storage 120.

At 202, the amount of internal memory allocated to the expandable databuffer and the amount of internal memory allocated to the expandablemapping table cache are adjusted based at least in part on the workloadlevel. For example, internal memory may be shifted from the expandablemapping table cache to the expandable data buffer (causing the former toshrink in size and the latter to expand in size), or vice versa. In someembodiments, the total amount of internal memory allocated to theexpandable mapping table cache and the expandable data buffer remainsconstant, even as the individual sizes of the two vary over time.

FIG. 3 is a diagram illustrating an embodiment of various allocations ofinternal memory to an expandable mapping table cache and an expandabledata buffer. For simplicity, the size of an entry in the expandable databuffer in this figure is the same size as an entry in the expandablemapping table cache.

In diagram 300, expandable mapping table cache (304 a) has a maximumnumber of cache entries (i.e., N_(max) ^(c)=10) allocated to it. Sincediagram 300 shows a low workload state, there are no occupied entries inthe expandable data buffer and there are two unoccupied entries (302 a)in the expandable data buffer. For example, if the expandable databuffer is a write buffer, then the scenario shown in diagram 300corresponds to no write data waiting to be written to the externalstorage (e.g., solid state storage on another semiconductor device). Putanother way, diagram 300 shows an example of no outstanding writes. Or,if the expandable data buffer is a read buffer, there have not beenrecent read instructions so there is no need to pre-fetch read data.Internal memory allocated for other purposes is shown as portion 306.This is one example of a low workload level and a correspondingallocation of internal memory.

In diagram 310, the amount of internal memory allocated to theexpandable mapping table cache has decreased compared to diagram 300,and the amount of internal memory allocated to the expandable databuffer has increased compared to diagram 300. In this example, there aretwo occupied entries in the expandable data buffer (308 b), twounoccupied entries in the expandable data buffer (302 b), and eightentries in the expandable mapping table cache (304 b). This is oneexample of a medium workload level and a corresponding allocation ofinternal memory. For example, if the data buffer is a write buffer, thenthe number of write instructions sent by the host may comprise only afew write instructions and/or the amount of write data sent by the hostmay be relatively small (e.g., short writes versus long writes).

In diagram 320, there are five occupied entries in the expandable databuffer (308 c), one unoccupied entry in the expandable data buffer (302c), and six entries in the expandable mapping table cache (304 c), whichis the minimum number of cache entries (i.e., N_(min) ^(c)=6). This isone example of a high workload level and a corresponding allocation ofinternal memory. For example, the host may have sent many writeinstructions and/or long (e.g., burst) write instructions.

FIG. 4 is a flowchart illustrating an embodiment of a process fordetermining a workload level. In some embodiments, step 200 in FIG. 2 isperformed in the following manner.

At 400, it is determined if a last write instruction is a long write.For example, in some systems, a host is able to perform a longsequential write, sometimes referred to as a block write or a burstwrite. In some embodiments, the amount of write data to be sent by thehost to the storage controller is specified at the beginning of the longsequential write (e.g., a predefined-length block write). Alternatively,the amount of write data may be unspecified and the end of thesequential write is signaled by a “stop” signal (e.g., an open-endedblock write). If the last write received from a host is such a longwrite, then the decision at step 400 is Yes.

If the last write instruction is a long write, than at 402 the workloadlevel is set to high. If the last write instruction is a short write,than at 404 the workload level is set to low.

FIG. 4 is merely exemplary and is not intended to be limiting. Forexample, the number or percentage of (un)occupied entries in the databuffer is described below as being used to adjust the amounts ofinternal memory allocated to the data buffer versus the cache (e.g., atstep 202 in FIG. 2). Naturally, some other embodiments may use thenumber or percentage of occupied entries in the data buffer whendetermining the workload level at step 200 in FIG. 2. Similarly, FIG. 4only has two workload levels: low and high. In various embodiments, anynumber of workload levels may be determined.

FIG. 5 is a flowchart illustrating an embodiment of a workload-based,internal memory reallocation process which takes into consideration hitcounts associated with cache entries that have been evicted. FIG. 5 issimilar to FIG. 2 and identical or similar reference numbers are usedfor related steps.

At 500, one or more hit counts associated with one or more cache entriesthat have been evicted from the expandable mapping table cache aretracked. In examples described herein, the hit counts are not trackingspecific logical-to-physical address mapping per se, but rather trackthe number of hits for the current set of (most recently) evicted cacheentries as that set varies over time. An example of this step isdescribed in further detail below.

At 200, a workload level associated with an expandable data buffer isdetermined, wherein the expandable data buffer and an expandable mappingtable cache are stored in internal memory and the expandable mappingtable cache is used to store a portion of a mapping table that is storedon external storage.

At 202 a, the amount of internal memory allocated to the expandable databuffer and the amount of internal memory allocated to the expandablemapping table cache are adjusted based at least in part on (1) theworkload level, (2) a minimum number of cache entries, (3), a maximumnumber of cache entries, and (4) the hit counts associated with thecache entries that have been evicted. Diagram 300 in FIG. 3 shows anexample of a maximum number of cache entries (in that example, N_(max)^(c)=10) and diagram 320 shows an example of a minimum number of cacheentries (in that example, N_(min) ^(c)=6). In some embodiments, step 202in FIG. 2 is performed in the manner described in step 202 a. An exampleof step 202 a is described in further detail below.

There are a number of benefits to the exemplary process shown in thisfigure. First, the minimum number of cache entries (N_(min) ^(c)) andthe maximum number of cache entries (N_(max) ^(c)) ensure that both theexpandable data buffer and the expandable mapping table cache never gobelow a first and second minimum size.

Second, taking into consideration hit counts associated with cacheentries that have been evicted is, conceptually speaking, like making aprediction or estimate of how many additional hits would be gained byadding additional entries to the expandable mapping table cache, andweighting that predicted benefit against the cost of shifting internalmemory from the data buffer to the cache. If the hit count(s) is/arezero or are very close to zero, then there is little predicted benefitin expanding the mapping table cache and it may not be worth theassociated cost (e.g., in processing resources, in power consumption,etc.) to expand the cache. Conversely, high hit count(s) corresponds toa prediction that there is a high utility or value in increasing thesize of the cache and as such suggests that shifting internal memory tothe cache from the data buffer is a worthwhile tradeoff.

FIG. 6 is a diagram illustrating an embodiment of hit counters and anassociated set of current, most recently evicted cache entries. The hitcounts tracked by hit counters 602 b are an example of the hit countswhich are tracked at step 500 in FIG. 5 and which are used to reallocateinternal memory at step 202 a.

In the example shown, the number of hit counters equals the maximumnumber of entries that can reside in a cache (i.e., N_(max) ^(c)). Assuch, there are N_(max) ^(c) cache entries in group 600 and N_(max) ^(c)hit counters in group 602. In some applications it is desirable to trackN_(max) ^(c) hit counts because there will be information available, forall cache sizes, to decide whether to expand the cache up to the maximumcache size (i.e., N_(max) ^(c)).

Each cache entry in group 600 stores a specific logical address tophysical address mapping. The cache entries in 600 a are the ones thatare currently in the cache where N^(c) (i.e., the number of entriescurrently in the cache) varies over time. For example, in diagram 300 inFIG. 3, N^(c)=10; in diagram 310, N^(c)=8; in diagram 320, N^(c)=6. Thecache entries in 600 b are the ones that have been most recently evictedfrom the cache. The cache entries in 600 are connected using a doublylinked list where the list is sorted according to access. Entry e₁ isthe most recently used cache entry (currently in the cache), e_(N) _(c)is the least recently used cache entry (currently in the cache), e_(N)_(c) ₊₁ is the entry most recently evicted from the cache, and e_(N)_(max) _(c) is the entry which was evicted from the cache the longesttime ago.

Hit counters 602 a are used to track hit counts for entries currently inthe cache and hit counters 602 b are used to track hit counts forentries which have been (most recently) evicted from the cache. The hitcounts tracked correspond to the respective locations or positionswithin the sorted list, not the specific logical address to physicaladdress mapping stored in an entry. To put it another way, the cacheentries in 600 are constantly being resorted but the hit counters in 602remain in the same order or sequence. Note, for example, that hitcounters 602 are not implemented as a doubly-linked list (unlike 600)because the hit counters will not be resorted or reordered and so doublelinks are not needed. The following figure describes an example of thisin more detail.

FIG. 7 is a diagram illustrating an embodiment of incremented hitcounters at various points in time. In the example shown, N_(max) ^(c)=5so hit counts are tracked for five entries total (i.e., some combinationof entries currently in the cache and entries evicted from the cache).To track which entries are in the cache and which entries have beenevicted from the cache, a least recently used (LRU) pointer (701) isused. The LRU pointer points to the least recently used entry that isstill in the cache. As such, the entry pointed to by the LRU pointer andall entries to the left of that entry are (currently) in the cache. Allentries strictly to the right of the LRU pointer have been evicted fromthe cache. For clarity, the number of entries in the cache (in thisexample, 3) and the number of entries evicted (in this example, 2) arekept constant throughout diagrams 700, 710, and 720 for clarity.

Diagram 700 shows the logical-to-physical address mappings stored in theentries and the hit counts at an exemplary point in time. A logicalblock address is then received from the host, for example as part of aread instruction or a write instruction. The received logical blockaddress is 67, which corresponds to entry 702 a in diagram 700, theleast recently used entry in the cache.

The corresponding hit counter is counter 704 a, which has a hit count of1 in diagram 700. That counter is incremented and as is shown in diagram710, count 704 b is now 2 to reflect the hit. As diagram 710 also shows,the logical-to-physical address mapping with a logical block address of67 has moved to the most recently used position (see, e.g., entry 702 bin diagram 710) and the other mappings have shifted to the right to makespace. Note that the hit counters do not rearrange themselves betweendiagrams 700 and 710 even though the logical-to-physical addressmappings have been rearranged.

Subsequently, after the state shown in diagram 710, the same logicalblock address of 67 is received again from the host. This time, theentry that has a logical block address of 67 is in the most recentlyused position (see, e.g., entry 702 b in diagram 710). As such, the hitcounter corresponding to the most recently used position is incrementedfrom 0 (see hit counter 706 b in diagram 710) to 1 (see hit counter 706c in diagram 720). Since the logical address received from the host isthe same as the last logical address received, the mapping with logicalblock address 67 remains at the head of the linked list as the mostrecently used entry (note, e.g., that MRU entry 702 b in diagram 710 andMRU entry 702 c in diagram 720 are the same).

As is shown in this example, the hit counters do not rearrangethemselves as the logical-to-physical address mappings do, but ratherthey track the number of hits for the logical-to-physical addressmapping which they currently correspond to. If the correspondinglogical-to-physical address mapping changes for a particular hitcounter, the hit counter does not move with that logical-to-physicaladdress mapping.

FIG. 8 is a flowchart illustrating an embodiment of a process fortracking hit counts. In some embodiments, step 500 in FIG. 5 isperformed in the following manner. In some embodiments, internal memorycontroller 118 in FIG. 1 performs the exemplary process. In someembodiments, the hit counts are stored in internal memory 112 in FIG. 1.

At 800, the type of update is determined. In this example, it isdetermined to increment a hit counter if a logical block address isreceived from a host, for example as part of a read instruction or awrite instruction. If it is determined to increment at 800, the hitcount corresponding to the cache entry that includes the receivedlogical block address is incremented at 802. See, for example, theexamples shown in FIG. 7.

If it is determined to increment at 800, all of the hit counts arehalved at 804. For example, in FIG. 7, all five hit counters (i.e.,corresponding to entries currently in the cache as well as evictedentries) would be cut in half. In some embodiments, it is determined atstep 800 to decrement a hit counter if a forgetting timer expires.

In some applications, halving all hit counts when a timer expires is anacceptable estimate because the quality of the results is “good enough”and the technique is not complicated and it does not require a lot ofinformation to be tracked. For example, one alternative is to track thetimestamps at which each hit counter is updated. This would enable thehit counts to perfectly reflect the number of hits for a specifiedwindow of time. However, storing the timestamp for each hit wouldrequire a lot of memory, which is undesirable since this technique islikely to be used in systems which have a limited amount of internalmemory.

Another alternative would be to zero out the hit counts when some timerexpires. However, this would be undesirable because if the system neededto make a decision about whether to expand the cache immediately afterthe hit counts were reset, then the system would have no informationavailable about the recent past and whether it might be worthwhile toexpand the cache.

As such, using a forgetting timer and halving the hit counts when thetimer expires may provide “good enough” results without being processingand/or memory intensive to implement.

FIG. 9 is a flowchart illustrating an embodiment of a process foradjusting an amount of internal memory allocated based at least in parton hit counts. In some embodiments, the process shown is used at step202 a in FIG. 5.

At 900, the workload level is checked. For example, the process of FIG.4 outputs a workload level of high or low depending upon the last writeinstruction. If the workload level is high, it is determined at 902 ifthe number of entries in the expandable mapping table cache (i.e.,N^(c)) is less than or equal to the minimum number of entries in theexpandable mapping table cache (i.e., N_(min) ^(c)). If so, the processends. If not, at least some internal memory is reallocated from theexpandable mapping table cache to the expandable write buffer at 904.

If the workload level at 900 is low, at 906 it is determined if thereare write buffers available. For example, if one or more entries in thewrite buffer have been unoccupied for some specified period of time,they may be considered free and available for reallocation to theexpandable mapping table cache. If not, the process ends.

If, however, there are write buffers available at 906, it is determinedif the number of entries in the expandable mapping table cache isgreater than or equal to the maximum number of entries in the expandablemapping table cache at 908. If so, the process ends.

If, however, the number of entries in the expandable mapping table cachehas not exceeded the maximum, at 910 the hit counts are used todetermine if a larger cache would improve the cache hit rate. Forexample, suppose three entries in the write buffer are determined to beavailable at 906. The hit count for the three most recently evictedentries are added and compared to a threshold (e.g., which may be scaledbased on the number of entries being considered). If the sum of the hitcounts is greater than a threshold, it is decided the cache hit ratewould be improved. If the sum is less than the threshold, then it isdecided that the cache hit rate would not be improved.

If the cache hit rate would be improved at 910, at least some internalmemory is reallocated from the expandable write buffer to the expandablemapping table cache at 912. To continue the example from above, thethree entries for which the sum of hit counts was used at step 910 wouldbe reallocated to the cache at step 912. If the cache hit rate would notbe improved at 910, then the process ends without reallocating internalmemory from the expandable write buffer to the expandable mapping tablecache because it is not worth the cost of performing the reallocation.

In some embodiments, a threshold used at step 910 is an adjustablethreshold. Using an adjustable threshold is desirable because then itcan be adjusted based on the associated cost of relocating internalmemory from a data buffer to the cache. In a system with a higherreallocation cost, the threshold is set to a higher value. In systemswhere the reallocation cost is lower, a lower threshold value is used.

When downsizing the expandable mapping table cache and expanding theexpandable data buffer, it may be desirable to have some entries readyto be discarded that are less expensive to discard. The followingfigures describe various embodiments of this which may make thereallocation process faster.

FIG. 10 is a diagram illustrating an embodiment of an LRU window whichincludes dirty entries and clean entries. In the example shown, adoubly-linked list of entries associated with an expandable mappingtable cache is shown. As described above, LRU pointer 1000 is used totrack which entries are currently in the cache and which entries havebeen evicted.

In addition to LRU pointer 1000, there is LRU-MRUW pointer 1002, whichis used to divide the entries which are currently in the cache into amost recently used (MRU) window (in this example, those entries to theleft of LRU-MRUW pointer 1002 and pointed to by LRU-MRUW pointer 1002)and an LRU window (in this example, those entries between LRU-MRUWpointer 1002 and LRU pointer 1000, excluding the entry pointed to byLRU-MRUW pointer 1002).

In some embodiments, the size of the MRU window (i.e., k) is a constantsize and the size of the LRU window varies as the cache size changes. Insome embodiments, the size of the MRU window (i.e., k) is selected suchthat k=N_(min) ^(c)−N_(evict) where N_(evict) is a desired number ofentries to evict (e.g., if the host sends down a long write, the numberof entries desired to be evicted from the cache).

Within the LRU window, the dirty entries and clean entries are sorted sothat the clean entries are closest to the evicted entries and the dirtyentries are closest to the MRU window. LRU-dirty pointer 1004 is used totrack the division between dirty entries and clean entries in the LRUwindow. As used herein, a dirty entry is one for which thelogical-to-physical address mapping stored in the cache (e.g., cache 116in FIG. 1) does not match the logical-to-physical address mapping storedon external storage (e.g., on mapping table 122 in FIG. 1). As such, ifa dirty entry is evicted from the cache (e.g., because that internalmemory is being reallocated to the data buffer), an update to theexternal storage will also be required. In contrast, a clean entry isone for which the logical-to-physical address mapping in the cache andthe external storage match. As such, no update to the mapping tablestored on external storage is needed.

When entries are evicted from the cache so that they can be used by thewrite buffer (or, more generally, the data buffer), the eviction is doneby moving LRU pointer 1000 the appropriate number of entries to theleft. As such, the first entries that will be evicted will be the cleanentries using the example implementation shown. Only when all of theclean entries have been evicted will the dirty entries start to beevicted. This is desirable because it may be possible to evict someentries from the cache without having to update the mapping table storedon external storage (e.g., which may delay some other access to theexternal storage).

In some embodiments, a process operates in the background to reorderentries in the doubly-linked list as entries in the LRU window becomedirty. In the event a clean entry becomes dirty (e.g., because thephysical address in a mapping in the cache changes, such that themapping in the cache no longer matches that in the external storage),that entry is removed from its location with the clean entries and ismoved with the dirty entries.

In some embodiments, to ensure that the supply of clean entries iscontinually refreshed, a cleanup process may commit changes in dirtyentries in the LRU window to the mapping table in external storage sothat an entry becomes clean. To obviate the need to rearrange entries inthe doubly-linked list, in some embodiments the entry pointed to byLRU-dirty pointer 1004 is the one for which changes are committed. Afterthe changes are committed to the mapping table in external memory, theLRU-dirty pointer is shifted one entry to the left without having torearrange the doubly-linked list. In some embodiments, such a cleanupprocess is initiated when the number of clean entries in the LRU windowis less than some threshold. In some embodiments, the cleanup processstops when the number of clean entries in the LRU window reaches anotherthreshold.

FIG. 11 is a flowchart illustrating an embodiment of a workload-based,internal memory reallocation process that uses a sorted, doubly-linkedlist. FIG. 11 is similar to FIG. 2 and identical or similar referencenumbers are used for related steps.

At 200, a workload level associated with an expandable data buffer isdetermined, wherein the expandable data buffer and an expandable mappingtable cache are stored in internal memory and the expandable mappingtable cache is used to store a portion of a mapping table that is storedon external storage.

At 1100, a doubly-linked list that includes the expandable mapping tablecache is sorted such that one or more clean entries in the expandablemapping table cache are in a position to be evicted before one or moredirty entries in the expandable mapping table cache would be evicted.See, for example, FIG. 10. In that example, the clean entries (i.e.,e_(m+1), . . . , e_(N) _(c) ) would be discarded first before the dirtyentries (i.e., e_(k+1), . . . , e_(m)).

At 202 b, the amount of internal memory allocated to the expandable databuffer and the amount of internal memory allocated to the expandablemapping table cache are adjusted based at least in part on the workloadlevel, including by using the sorted, doubly-linked list. For example,if one or more entries in the expandable mapping table cache need to beevicted, then in the example of FIG. 11, the LRU pointer 1000 would beshifted to the left, such that the clean entries would be evicted first,followed by the dirty entries.

In some embodiments, the dirty entries within an LRU window are sortedbased on some criteria so that less costly dirty entries are evictedbefore more expensive dirty entries. The following describes one suchexample.

FIG. 12 is a diagram illustrating an embodiment of dirty page countswhich are used to sort dirty entries in an LRU window. In the exampleshown, dirty entries 1200 and 1202 are being evaluated so they can besorted within an LRU window so that dirty entries that are lessexpensive (or otherwise preferable in some manner) are evicted beforemore expensive dirty entries. For example, in FIG. 10, the entries inthe LRU window may be sorted so that entry e_(m) is the least expensiveentry to evict, entry e_(m−1) is the second least expensive entry toevict, and so on.

Dirty entry 1200 is stored in block 1252 on solid state storage 1250 anddirty entry 1202 is stored in block 1254. In this example, each blockincludes four pages and (for convenience) each cache entry (i.e., eachlogical-to-physical address mapping) occupies a page. Each page in theblock has a dirty bit associated with it, indicating whether that pageis dirty and thus is out of date. If dirty entry 1200 were discardedfrom the cache, then the dirty bit corresponding to page 1256 in block1252 would be set. In contrast, if dirty entry 1202 were discarded fromthe cache, then the dirty bit corresponding to page 1258 in block 1254would be set. In this example, the dirty bits have not been set forpages 1256 and 1258 because pages in solid state storage 1250 are notmarked as dirty until the change is committed or otherwise communicatedfrom the cache to the solid state storage (e.g., because a particularlogical-to-physical address mapping has been evicted from the cache, orbecause dirty entries in the cache are being proactively committed tosolid state storage in order to become clean entries so that if a longwrite command comes down from the host there will be sufficient cleanentries in the cache to evict quickly and/or easily).

From the state of dirty bits shown, the dirty bit count for entry 1200is 0 and the dirty bit count for entry 1202 is 3. The dirty bit countsare used in this example to decide what order dirty entries 1200 and1202 should be in. To put it another way, the dirty bit counts are usedto sort dirty entries in the LRU window so that the order reflects somemetric or cost.

In some embodiments, the system is configured to be in a “reclamation”mode where the system attempts to discard pages first that will cause agarbage collection or other reclamation process to be triggered. Forexample, if dirty entry 1202 were discarded, then all of the pages inblock 1254 would be marked as dirty and a reclamation process couldreclaim block 1254 for use. As such, in some cases it may be desirableto discard dirty pages with higher dirty bit counts before those withlower dirty bit counts and the LRU window is sorted accordingly.

In some embodiments, the system is configured to be in an “avoidreclamation” mode where the system attempts to delay or avoid garbagecollection or other reclamation processes until absolutely necessary(e.g., for power consumption reasons). For example, if dirty entry 1200were discarded, then only one page in block 1252 would be dirty and thenumber of dirty pages may be low enough so that a garbage collection orother reclamation process is not (e.g., automatically) triggered. Inthis configuration, dirty pages with lower dirty bit counts arediscarded before those with higher dirty bit counts and the LRU windowis sorted accordingly.

Although the foregoing embodiments have been described in some detailfor purposes of clarity of understanding, the invention is not limitedto the details provided. There are many alternative ways of implementingthe invention. The disclosed embodiments are illustrative and notrestrictive.

What is claimed is:
 1. A system, comprising: an internal memoryincluding an expandable data buffer and an expandable mapping tablecache; and an internal memory controller configured to: determine aworkload level associated with the expandable data buffer, wherein theexpandable data buffer and the expandable mapping table cache are storedin internal memory and the expandable mapping table cache is used tostore a portion of a mapping table that is stored on external storage,the workload level is set to high if a last write instruction is a longwrite and the workload level is set to low if the last write instructionis a short write; and adjust an amount of internal memory allocated tothe expandable data buffer and an amount of internal memory allocated tothe expandable mapping table cache based at least in part on theworkload level.
 2. The system of claim 1, wherein the system includes asemiconductor device, including one or more of the following: anapplication-specific integrated circuit (ASIC) or a field-programmablegate array (FPGA).
 3. The system of claim 1 further comprising theexternal storage that includes the mapping table.
 4. The system of claim1, wherein: the internal memory controller is further configured totrack one or more hit counts associated with one or more cache entriesthat have been evicted from the expandable mapping table cache; and theinternal memory controller is configured to adjust further based atleast in part on: a minimum number of cache entries, a maximum number ofcache entries, and the hit counts associated with the cache entries thathave been evicted.
 5. The system of claim 4, wherein the internal memorycontroller is configured to track, including by: determining a type ofupdate, wherein: in the event a logical block address is received from ahost, it is determined to increment; and in the event a forgetting timerexpires, it is determined to decrement; in the event it is determined toincrement, incrementing a hit count corresponding to a cache entry thatincludes the received logical block address; and in the event it isdetermined to decrement, halving all of the hit counts.
 6. The system ofclaim 1, wherein: the internal memory controller is further configuredto sort a doubly-linked list that includes the expandable mapping tablecache such that one or more clean entries in the expandable mappingtable cache are in a position to be evicted before one or more dirtyentries in the expandable mapping table cache would be evicted; and theinternal memory controller is configured to adjust, including by usingthe sorted doubly-linked list.
 7. The system of claim 6, wherein theinternal memory controller is further configured to sort the dirtyentries using a dirty page count.
 8. A method, comprising: using aprocessor to determine a workload level associated with an expandabledata buffer, wherein the expandable data buffer and an expandablemapping table cache are stored in internal memory and the expandablemapping table cache is used to store a portion of a mapping table thatis stored on external storage, the workload level is set to high if alast write instruction is a long write and the workload level is set tolow if the last write instruction is a short write; and using theprocessor to adjust an amount of internal memory allocated to theexpandable data buffer and an amount of internal memory allocated to theexpandable mapping table cache based at least in part on the workloadlevel.
 9. The method of claim 8, wherein the method is performed by asemiconductor device, including one or more of the following: anapplication-specific integrated circuit (ASIC) or a field-programmablegate array (FPGA).
 10. The method of claim 8, wherein: the methodfurther includes tracking one or more hit counts associated with one ormore cache entries that have been evicted from the expandable mappingtable cache; and using the processor to adjust the amount of internalmemory allocated to the expandable data buffer and the amount ofinternal memory allocated to the expandable mapping table cache isfurther based at least in part on: a minimum number of cache entries, amaximum number of cache entries, and the hit counts associated with thecache entries that have been evicted.
 11. The method of claim 10,wherein tracking includes: determining a type of update, wherein: in theevent a logical block address is received from a host, it is determinedto increment; and in the event a forgetting timer expires, it isdetermined to decrement; in the event it is determined to increment,incrementing a hit count corresponding to a cache entry that includesthe received logical block address; and in the event it is determined todecrement, halving all of the hit counts.
 12. The method of claim 8,wherein: the method further includes sorting a doubly-linked list thatincludes the expandable mapping table cache such that one or more cleanentries in the expandable mapping table cache are in a position to beevicted before one or more dirty entries in the expandable mapping tablecache would be evicted; and using the processor to adjust the amount ofinternal memory allocated to the expandable data buffer and the amountof internal memory allocated to the expandable mapping table cachefurther includes using the sorted doubly-linked list.
 13. The method ofclaim 12 further comprising sorting the dirty entries using a dirty pagecount.
 14. A computer program product, the computer program productbeing embodied in a non-transitory computer readable storage medium andcomprising computer instructions for: determining a workload levelassociated with an expandable data buffer, wherein the expandable databuffer and an expandable mapping table cache are stored in internalmemory and the expandable mapping table cache is used to store a portionof a mapping table that is stored on external storage, the workloadlevel is set to high if a last write instruction is a long write and theworkload level is set to low if the last write instruction is a shortwrite; and adjusting an amount of internal memory allocated to theexpandable data buffer and an amount of internal memory allocated to theexpandable mapping table cache based at least in part on the workloadlevel.
 15. The computer program product of claim 14, wherein: thecomputer program product further includes computer instructions fortracking one or more hit counts associated with one or more cacheentries that have been evicted from the expandable mapping table cache;and the computer instructions for adjusting the amount of internalmemory allocated to the expandable data buffer and the amount ofinternal memory allocated to the expandable mapping table cache furtherinclude computer instructions for adjusting based at least in part on: aminimum number of cache entries, a maximum number of cache entries, andthe hit counts associated with the cache entries that have been evicted.16. The computer program product of claim 15, wherein the computerinstructions for tracking include computer instructions for: determininga type of update, wherein: in the event a logical block address isreceived from a host, it is determined to increment; and in the event aforgetting timer expires, it is determined to decrement; in the event itis determined to increment, incrementing a hit count corresponding to acache entry that includes the received logical block address; and in theevent it is determined to decrement, halving all of the hit counts. 17.The computer program product of claim 14, wherein: the computer programproduct further includes computer instructions for sorting adoubly-linked list that includes the expandable mapping table cache suchthat one or more clean entries in the expandable mapping table cache arein a position to be evicted before one or more dirty entries in theexpandable mapping table cache would be evicted; and the computerinstructions for adjusting the amount of internal memory allocated tothe expandable data buffer and the amount of internal memory allocatedto the expandable mapping table cache further include computerinstructions for using the sorted doubly-linked list.
 18. The computerprogram product of claim 17 further comprising computer instructions forsorting the dirty entries using a dirty page count.